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Ge-based Channel MOSFETs

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Release : 2011-10
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Kind : eBook
Book Rating : 868/5 ( reviews)

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Book Synopsis Ge-based Channel MOSFETs by : Se-hoon Lee

Download or read book Ge-based Channel MOSFETs written by Se-hoon Lee. This book was released on 2011-10. Available in PDF, EPUB and Kindle. Book excerpt: This work presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology.

Germanium-Based Technologies

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Release : 2011-07-28
Genre : Science
Kind : eBook
Book Rating : 90X/5 ( reviews)

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Book Synopsis Germanium-Based Technologies by : Cor Claeys

Download or read book Germanium-Based Technologies written by Cor Claeys. This book was released on 2011-07-28. Available in PDF, EPUB and Kindle. Book excerpt: Germanium is a semiconductor material that formed the basis for the development of transistor technology. Although the breakthrough of planar technology and integrated circuits put silicon in the foreground, in recent years there has been a renewed interest in germanium, which has been triggered by its strong potential for deep submicron (sub 45 nm) technologies. Germanium-Based technologies: From Materials to Devices is the first book to provide a broad, in-depth coverage of the field, including recent advances in Ge-technology and the fundamentals in material science, device physics and semiconductor processing. The contributing authors are international experts with a world-wide recognition and involved in the leading research in the field. The book also covers applications and the use of Ge for optoelectronics, detectors and solar cells. An ideal reference work for students and scientists working in the field of physics of semiconductor devices and materials, as well as for engineers in research centres and industry. Both the newcomer and the expert should benefit from this unique book. State-of-the-art information available for the first time as an all-in-source Extensive reference list making it an indispensable reference book Broad coverage from fundamental aspects up to industrial applications

Simulation and Design of Germanium-based Mosfets for Channel Lengths of 100 Nm and BelowW

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Release : 2007
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Book Synopsis Simulation and Design of Germanium-based Mosfets for Channel Lengths of 100 Nm and BelowW by :

Download or read book Simulation and Design of Germanium-based Mosfets for Channel Lengths of 100 Nm and BelowW written by . This book was released on 2007. Available in PDF, EPUB and Kindle. Book excerpt: The purpose of this study is to examine the performance capabilities and scaling behavior of short channel Ge-based n-MOSFETs using a commercial numerical device simulator from ISE Corporation. This thesis will describe the results of DC and small signal AC simulations of the devices transistor characteristics and compare them with those for a silicon device of the same geometry and size. We will also examine the effects of variations in the device structure on the Ge MOSFETs performance, including the transconductance and high frequency response.

Process Integration and Performance Evaluation of Ge-based Quantum Well Channel MOSFETs for Sub-22nm Node Digital CMOS Logic Technology

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Release : 2011
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Book Synopsis Process Integration and Performance Evaluation of Ge-based Quantum Well Channel MOSFETs for Sub-22nm Node Digital CMOS Logic Technology by : Se-Hoon Lee

Download or read book Process Integration and Performance Evaluation of Ge-based Quantum Well Channel MOSFETs for Sub-22nm Node Digital CMOS Logic Technology written by Se-Hoon Lee. This book was released on 2011. Available in PDF, EPUB and Kindle. Book excerpt: Since metal-oxide-semiconductor (MOS) device was first reported around 1959 and utilized for integrated circuits in 1961, complementary MOS technology has become the mainstream of semiconductor industry. Its performance has been improved based on scaling of dimensions of MOS field-effect-transistors (MOSFET) in accordance with Moore's law, which states that the density of MOSFETs due to scaling approximately doubles every two years. Entering into sub-100nm regime caused a lot of challenges. Traditional way of scaling no longer provided performance enhancement of individual MOSFETs. Increased channel doping which is required to prevent degradation of device electrostatics from short channel effects caused carrier mobility degradation. New inventions needed to be incorporated to sustain performance enhancement trend with scaling. Implementation of process induced strained Si technology allowed mobility enhancement, and high-K/metal gate instead of conventional poly-Si/SiO2 allowed continuing electrical gate oxide thickness scaling, hence extending the life span of Moore's law. As we are now moving toward 22nm logic technology and below, new concerns have been rapidly aroused. Controlling power consumption and performance variability are becoming as important as developing scaled devices with enhanced performance. Expandability of strained-Si channel technology via process induced strain also faces increasing complexity from ever tighter gate pitch and difficulties in controlling defect level with the channel stress enhancement techniques. At the same time, long-lasting planar MOSFET architecture also faces serious challenges due to the limits of controlling short channel effects. New paradigms and pathways for future technology seems to be required. As a result, new material sets, new device architectures and concepts are being vigorously explored in the literature. These new trends can be categorized into three groups: MOSFET structure with (non-Si) high mobility channel materials, advanced (non-planar) MOSFET structures, and MOSFET-type structures with new device operation concepts such as tunneling FETs. This dissertation presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology.

Interface-engineered Ge MOSFETs for Future High Performance CMOS Applications

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Author :
Release : 2009
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Book Synopsis Interface-engineered Ge MOSFETs for Future High Performance CMOS Applications by : Duygu Kuzum

Download or read book Interface-engineered Ge MOSFETs for Future High Performance CMOS Applications written by Duygu Kuzum. This book was released on 2009. Available in PDF, EPUB and Kindle. Book excerpt: As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, introduction of performance boosters like novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge has particularly become of great interest as a channel material, owing to its high bulk hole and electron mobilities. However, replacement of Si channel by Ge requires several critical issues to be addressed in Ge MOS technology. High quality gate dielectric for surface passivation, low parasitic source/drain resistance and performance improvement in Ge NMOS are among the major challenges in realizing Ge CMOS. Detailed characterization of gate dielectric/channel interface and a deeper understanding of mobility degradation mechanisms are needed to address the Ge NMOS performance problem and to improve PMOS performance. In the first part of this dissertation, the electrical characterization results on Ge NMOS and PMOS devices fabricated with GeON gate dielectric are presented. Carrier scattering mechanisms are studied through low temperature mobility measurements. For the first time, the effect of substrate crystallographic orientation on inversion electron and hole mobilities is investigated. Direct formation of a high-k dielectric on Ge has not given good results in the past. A good quality interface layer is required before the deposition of a high-K dielectric. In the second part of this dissertation, ozone-oxidation process is introduced to engineer Ge/insulator interface. Electrical and structural characterizations and stability analysis are carried out and high quality Ge/dielectric interface with low interface trap density is demonstrated. Detailed extraction of interface trap density distribution across the bandgap and close to band edges of Ge, using low temperature conductance and capacitance measurements is presented. Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups worldwide. In spite of the increasing interest in Ge, the major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In the last part of this dissertation, the results on Ge NMOS devices fabricated with the ozone-oxidation and the low temperature source/drain activation processes are discussed. These devices achieve the highest electron mobility to-date, about 1.5 times the universal Si mobility. Detailed interface characterizations, trapping analyses and gated Hall device measurements are performed to identify the mechanisms behind poor Ge NMOS performance in the past.

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