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Fast High-order Variation-aware IC Interconnect Analysis

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Release : 2010
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Book Synopsis Fast High-order Variation-aware IC Interconnect Analysis by : Xiaoji Ye

Download or read book Fast High-order Variation-aware IC Interconnect Analysis written by Xiaoji Ye. This book was released on 2010. Available in PDF, EPUB and Kindle. Book excerpt: Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this thesis, three practical interconnect delay and slew analysis methods are presented to facilitate efficient evaluation of wire performance variability. The first method is described in detail in Chapter III. It harnesses a collection of computationally efficient procedures and closed-form formulas. By doing so, process variations are directly mapped into the variability of the output delay and slew. This method can provide the closed-form formulas of the output delay and slew at any sink node of the interconnect nets fully parameterized, in-process variations. The second method is based on adjoint sensitivity analysis and driving point model. It constructs the driving point model of the driver which drives the interconnect net by using the adjoint sensitivity analysis method. Then the driving point model can be propagated through the interconnect network by using the first method to obtain the closedform formulas of the output delay and slew. The third method is the generalized second-order adjoint sensitivity analysis. We give the mathematical derivation of this method in Chapter V. The theoretical value of this method is it can not only handle this particular variational interconnect delay and slew analysis, but it also provides an avenue for automatical linear network analysis and optimization. The proposed methods not only provide statistical performance evaluations of the interconnect network under analysis but also produce delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. Experimental results show that superior accuracy can be achieved by our proposed methods.

IC Interconnect Analysis

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Release : 2007-05-08
Genre : Technology & Engineering
Kind : eBook
Book Rating : 710/5 ( reviews)

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Book Synopsis IC Interconnect Analysis by : Mustafa Celik

Download or read book IC Interconnect Analysis written by Mustafa Celik. This book was released on 2007-05-08. Available in PDF, EPUB and Kindle. Book excerpt: As integrated circuit (IC) feature sizes scaled below a quarter of a micron, thereby defining the deep submicron (DSM) era, there began a gradual shift in the impact on performance due to the metal interconnections among the active circuit components. Once viewed as merely parasitics in terms of their relevance to the overall circuit behavior, the interconnect can now have a dominant impact on the IC area and performance. Beginning in the late 1980's there was significant research toward better modeling and characterization of the resistance, capacitance and ultimately the inductance of on-chip interconnect. IC Interconnect Analysis covers the state-of-the-art methods for modeling and analyzing IC interconnect based on the past fifteen years of research. This is done at a level suitable for most practitioners who work in the semiconductor and electronic design automation fields, but also includes significant depth for the research professionals who will ultimately extend this work into other areas and applications. IC Interconnect Analysis begins with an in-depth coverage of delay metrics, including the ubiquitous Elmore delay and its many variations. This is followed by an outline of moment matching methods, calculating moments efficiently, and Krylov subspace methods for model order reduction. The final two chapters describe how to interface these reduced-order models to circuit simulators and gate-level timing analyzers respectively. IC Interconnect Analysis is written for CAD tool developers, IC designers and graduate students.

Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide

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Release : 2014-10-15
Genre : Technology & Engineering
Kind : eBook
Book Rating : 732/5 ( reviews)

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Book Synopsis Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide by : Trent McConaghy

Download or read book Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide written by Trent McConaghy. This book was released on 2014-10-15. Available in PDF, EPUB and Kindle. Book excerpt: This book targets custom IC designers who are encountering variation issues in their designs, especially for modern process nodes at 45nm and below, such as statistical process variations, environmental variations, and layout effects. It teaches them the state-of-the-art in Variation-Aware Design tools, which help the designer to analyze quickly the variation effects, identify the problems, and fix the problems. Furthermore, this book describes the algorithms and algorithm behavior/performance/limitations, which is of use to designers considering these tools, designers using these tools, CAD researchers, and CAD managers.

Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits

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Release : 2010
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Book Synopsis Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits by : Suryanarayana Pendela

Download or read book Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits written by Suryanarayana Pendela. This book was released on 2010. Available in PDF, EPUB and Kindle. Book excerpt: Much of the Semiconductor Industry's success can be attributed to Moore's law which states that the number of transistors on an integrated circuit would double approximately every two years. Semiconductor industry has ever since progressed from designs with a few hundred transistors to today's complex designs incorporating millions of transistors. The current era of nanometer technologies threatens to impact the sustainability of Moore's law with random variations in the manufacturing process impacting yield in a big way. Considerable research efforts have since been devoted to account for these variations leading to a new paradigm called Design for Manufacturing (DFM). Traditional Static Timing Analysis (STA) has given way to Statistical Static Timing Analysis (SSTA) techniques wherein the parameters considered are treated as random variables with assigned probability distribution functions. However, SSTA is still not seen as a mature flow for commercial adoption, owing to the inherent complex nature of the SSTA algorithms. In this thesis, we propose an alternate framework to STA under the presence of process variations using Interval Valued Static Timing Analysis (IVSTA). Process variations are accounted for by using a macro-modeling framework providing an efficient and fast timing analysis technique. Results on standard benchmarks show that IVSTA can predict the timing slack by a margin of 5-10% error and huge improvement of runtime compared to traditional corner based analysis. The framework involves a one-time characterization of the standard cell library and can be incorporated without much modification to the design flow. An iterative optimization framework using IVSTA engine is also presented which optimizes a routed netlist for variations at a minimum penalty of area and power.

Interconnect Analysis and Synthesis

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Release : 2000
Genre : Computers
Kind : eBook
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Book Synopsis Interconnect Analysis and Synthesis by : Chung-Kuan Cheng

Download or read book Interconnect Analysis and Synthesis written by Chung-Kuan Cheng. This book was released on 2000. Available in PDF, EPUB and Kindle. Book excerpt: State-of-the-art methods and current perspectives on interconnect The irrepressible march toward smaller and faster integrated circuits has made interconnect a hot topic for semiconductor research. The effects of wire size, topology construction, and network design on system performance and reliability have all been thoroughly investigated in recent years. Interconnect Analysis and Synthesis provides CAD researchers and engineers with powerful, state-of-the-art tools for the analysis, design, and optimization of interconnect. It brings together a wealth of information previously scattered throughout the literature, explaining in depth available analysis techniques and presenting a range of CAD algorithms for synthesizing and optimizing interconnect. Along with examples and results from the semiconductor industry and 150 illustrations, this practical work features: Models for interconnect as well as devices and the impact of scaling trends Modern analysis techniques, from matrix reduction and moment matching to transmission-line analysis An overview of the effects of inductance on on-chip interconnect Flexible CAD algorithms that can be generalized for different needs, from buffer insertion to wire sizing to routing topology Emphasis on realistic problem formulations, addressing key design tradeoffs such as those between area and performance

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