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Prospects of Germanium-based MOSFETs and Tunnel Transistors for Low Power Digital Logic

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Release : 2017
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Book Synopsis Prospects of Germanium-based MOSFETs and Tunnel Transistors for Low Power Digital Logic by : Winston Chern

Download or read book Prospects of Germanium-based MOSFETs and Tunnel Transistors for Low Power Digital Logic written by Winston Chern. This book was released on 2017. Available in PDF, EPUB and Kindle. Book excerpt: Moore's law has driven technological improvements for decades by halving the areal footprint of the transistor every two years and increasing the performance of making integrated circuits while reducing their cost. The ability to reduce the footprint of the device was enabled by advances in processing technology, novel materials and device design. As ever-smaller footprints are desired, power density limitations and performance degradation require more innovations on all fronts. Recently introduced improvements to integrated circuits are high-K and metal gate for MOSFETs (45-nm node onward), the FinFET (22-nm node onward) and air gaps between copper interconnects (14-nm node) illustrating that at every new technology node there needs to be a materials or process-related improvement to reduce power and maintain performance. Other approaches are also being explored or taken to further improve the MOSFET performance in future technology nodes, namely use of channel materials with higher carrier mobility such as SiGe and Ge for p-MOSFETs, III-V compound semiconductors for n-MOSFETs and steep subthreshold swing devices such as tunnel field effect transistors (TFETs). This work evaluates both approaches utilizing germanium (Ge) and strained-Ge as a material to understand the benefits and drawbacks to both approaches. Hypothetically, high carrier mobility and velocity channel materials can lower the overall power consumption because lower power supply voltage is required to obtain the same amount of current. Germanium and strained-Ge are candidates for the channel material of p-MOSFETs. MOSFETs made using Ge and strained-Ge as the channel material are evaluated based upon the ITRS roadmap requirements using experimental results in this work and data from literature. The approach for using TFETs was evaluated in this work also using germanium as a channel material. TFETs can have a steep subthreshold swing (SS), better than the minimum of 60 mV/decade at room temperature for a MOSFET, which also reduces the total power and supply voltage required for operation. The reduced SS is hypothetically achieved through the band-to-band tunneling which allows for the filtering of the Fermi-tail distribution of carriers. Experimentally, TFETs have not generally shown the steeper than Fermi-tail SS promised by the theory and this work uses both results from fabricated strained-Si/strained-Ge TFETs as well as modeling to explain why this has been the case. The challenges for both technologies are outlined in this thesis and suggestions are made on approaches to tackling their respective intrinsic problems from the point of view of Ge-based devices.

Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic

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Release : 2012
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Book Synopsis Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic by : Sung Hwan Kim

Download or read book Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic written by Sung Hwan Kim. This book was released on 2012. Available in PDF, EPUB and Kindle. Book excerpt: Driven by a strong demand for mobile and portable electronics, the chip market will undoubtedly impose "low power" as the key metric for microprocessor design. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) operating principle and its immutable physics: an injection of thermally distributed carriers will not allow for switching characteristics better than 60 mV/dec at room temperature. This constraint ultimately defines the lowest energy consumed per digital operation attainable with current Complementary-Metal-Oxide-Semiconductor (CMOS) technology. In this work, Tunnel Field Effect Transistor (TFET) based on Band-to-Band Tunneling (BTBT) will be proposed and investigated as an alternative logic switch which can achieve steeper switching characteristics than the MOSFET to permit for lower threshold (V TH) and supply voltage (V DD) operation. It will be experimentally demonstrated that by employing Germanium (Ge) only in the source region of the device, a record high on to off current ratio (I ON /I OFF) can be obtained for 0.5 V operation. Technology Computer Aided Design (TCAD) calibrated to the measured data will be used to perform design optimization study. The performance of the optimized Ge-source TFET will be benchmarked against CMOS technology to show greater than 10x improvement in the overall energy efficiency for frequency range up to 500 MHz. The fundamental challenges associated with TFET-based digital logic design will be addressed. In order to mitigate these constraints, a circuit-level solution based on n-channel TFET Pass-Transistor Logic (PTL) will be proposed and demonstrated through mixed-mode simulations. The accompanying design modifications required at the device level will be discussed.

Tunneling Field Effect Transistors

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Release : 2023-06-08
Genre : Technology & Engineering
Kind : eBook
Book Rating : 825/5 ( reviews)

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Book Synopsis Tunneling Field Effect Transistors by : T. S. Arun Samuel

Download or read book Tunneling Field Effect Transistors written by T. S. Arun Samuel. This book was released on 2023-06-08. Available in PDF, EPUB and Kindle. Book excerpt: This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications. Tunneling Field Effect Transistors: Design, Modeling and Applications brings researchers and engineers from various disciplines of the VLSI domain to together tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications, and it also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains such as nanoelectronics, Memory Devices, and biosensing applications. They also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon. The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Advanced Nanoscale MOSFET Architectures

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Release : 2024-07-03
Genre : Technology & Engineering
Kind : eBook
Book Rating : 943/5 ( reviews)

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Book Synopsis Advanced Nanoscale MOSFET Architectures by : Kalyan Biswas

Download or read book Advanced Nanoscale MOSFET Architectures written by Kalyan Biswas. This book was released on 2024-07-03. Available in PDF, EPUB and Kindle. Book excerpt: Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs. Additional topics covered include: High-k gate dielectrics and metal gate electrodes for multi-gate MOSFETs, covering gate stack processing and metal gate modification Strain engineering in 3D complementary metal-oxide semiconductors (CMOS) and its scaling impact, and strain engineering in silicon–germanium (SiGe) FinFET and its challenges and future perspectives TCAD simulation of multi-gate MOSFET, covering model calibration and device performance for analog and RF applications Description of the design of an analog amplifier circuit using digital CMOS technology of SCL for ultra-low power VLSI applications Advanced Nanoscale MOSFET Architectures helps readers understand device physics and design of new structures and material compositions, making it an important resource for the researchers and professionals who are carrying out research in the field, along with students in related programs of study.

Si/Ge Heterojunction Tunnel FETs for Low Power Applications and Junction Engineering in Germanium MOSFETs for High Performance Applications

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Release : 2016
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Book Synopsis Si/Ge Heterojunction Tunnel FETs for Low Power Applications and Junction Engineering in Germanium MOSFETs for High Performance Applications by : William Hsu (Ph. D.)

Download or read book Si/Ge Heterojunction Tunnel FETs for Low Power Applications and Junction Engineering in Germanium MOSFETs for High Performance Applications written by William Hsu (Ph. D.). This book was released on 2016. Available in PDF, EPUB and Kindle. Book excerpt: Power dissipation has become one of the most significant impediments to continued scaling of complementary metal-oxide-semiconductor (CMOS) technology. Two approaches have been proposed for enabling supply power scaling: (i) reduction of subthreshold swing (SS) with novel operation mechanisms, and (ii) increasing of ON-current with high mobility materials or advanced device architectures. In this work, two alternative devices, tunnel field-effect transistors (TFETs) and Ge-channel MOSFETs, are being explored as possible solutions to these two approaches, respectively. TFETs have the potential to achieve a SS steeper than the thermionic emission defined limit of 60 mV/dec at room temperature to which MOSFETs are subject and, thus, enable lower voltage, lower power logic. On the other hand, Ge is promising as the enabler for high mobility channel, offering the potential to further enhance ON-current. The compatibility with conventional Si CMOS manufacturing makes Ge very attractive compared to other high mobility materials (e.g. III-V). In the first part, a Si-technology compatible Si/Ge heterojunction TFET is proposed. The device design utilizes a strained-Si/strained-Ge vertical heterojunction to provide a staggered-gap band alignment with small effective band gap and gate normal tunneling. Performance evaluation by simulation suggests that the device has the potential to be competitive with modern MOSFETs. In addition, device design guidelines in terms of electrostatic control are discussed while considering the quantum effects. In the second part, we focus on source/drain junction engineering for Ge CMOS. For n-type junctions, advanced activation scheme using non-melt sub-millisecond laser spike annealing is utilized to demonstrate excellent diffusion control and high activation level. For p-type junctions, novel BF implantation is shown to offer a higher B activation level and a shallower junction depth in Ge as compared to B and BF2 implantations. The detail diffusion mechanism of B in the presence of F is studied. High performance Ge n-type and p-type diodes are obtained along with significant reduction of contact resistance, and integration in a MOSFET process flow.

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