Author : Jonah Caplan
Release : 2016
Genre :
Kind : eBook
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Book Synopsis Analysis and Code Generation for Multicore Fault Tolerant Mixed Criticality Embedded Systems by : Jonah Caplan
Download or read book Analysis and Code Generation for Multicore Fault Tolerant Mixed Criticality Embedded Systems written by Jonah Caplan. This book was released on 2016. Available in PDF, EPUB and Kindle. Book excerpt: "Safety critical embedded systems often require redundant hardware to guarantee correct operation. Typically, in the automotive domain, redundancy is implemented using a pair of cores executing in lockstep to achieve dual modular redundancy. Lockstep execution, however, has been shown in theory to be less efficient than alternative redundancy schemes such as on-demand redundancy, where redundancy is achieved by replicating threads in a multicore system. In this thesis, an analysis and code generation framework is presented which automates the porting of Simulink generated code to a previously implemented multicore architecture supporting ODR with fingerprinting hardware to detect errors.The framework consists of three stages: first a profiling stage where information is collected on execution time, then a mapping and scheduling phase where resources are allocated in a safe manner, and finally the generation of the code itself. A framework has been implemented to allow arbitrary intraprocedural analysis to be defined for a program compiled for the Nios II architecture. An analysis has been implemented using the framework to determine the worst case behaviour of loops. The instruction-accurate worst case execution time (WCET) of each function is then estimated using the standard implicit path enumeration technique. A novel four mode multicore schedulability analysis is presented for mixed criticality fault tolerant systems which improves the quality of service in the presence of faults or execution time overruns. The schedulability analysis is integrated with a design space exploration framework that uses genetic algorithms to determine schedules with better quality of service. Code generation targets a previously designed multicore platform with Nios II processors and fingerprinting based error detection to automate the porting of Simulink generated control algorithms onto the platform. The generated code is verified on a virtual model of the platform implemented with Open Virtual Platform. Future work will include verifying the code on FPGA and calibrate the WCET estimation to reflect non-ideal memory retrieval." --
